NextSilicon's Maverick-2 dataflow engine is a novel approach to computing, designed to revolutionize the way we process data. It aims to address the limitations of traditional CPUs and GPUs by offering a reconfigurable dataflow engine that can adapt to various computing tasks. This technology is backed by a team of experts, including Ilan Tayari, co-founder and vice president of architecture, who brings experience from Mellanox and Nvidia.
The Maverick-2 engine is a 64-bit dataflow processor that can be paired with NextSilicon's Arbel RISC-V processor to create 'superchips' for high-performance computing (HPC) applications. The combination of these two processors represents a significant advancement in architecture, appealing to HPC centers that prioritize 64-bit floating-point computing.
One of the key advantages of the Maverick-2 is its ability to automate code porting, execution, and optimization. It uses a multi-tier computing architecture with a reconfigurable dataflow engine at its core, allowing for efficient processing of HPC simulations and models. The dataflow engine maps instructions to ALUs (Arithmetic Logic Units) directly, eliminating the need for complex instruction handling and data shuffling, which are common in traditional CPUs.
The Maverick-2 chip features a grid of compute blocks, each containing hundreds of ALUs, enabling high-performance computing with thousands of threads running at 1.5 GHz. This architecture is designed to achieve high utilization rates for ALUs and FPUs, ensuring efficient resource allocation. The chip's design also includes a reservation station and dispatcher, which are patented features that optimize data flow and reduce overhead.
NextSilicon's dataflow architecture is praised for its lower overhead compared to CPUs and GPUs. It dedicates most resources to actual computation, minimizing instruction handling and data movement. This approach allows for fully utilized compute units and reduces latency, making it an attractive solution for HPC applications.
The Arbel RISC-V processor complements the Maverick-2, offering a fully integrated CPU solution without the licensing fees associated with other processors. It features a homegrown RISC-V core with a 10-wide issue decoder and six ALUs on the integer side, along with four 128-bit FPUs on the vector side. The Arbel core can support 16 scalar instructions in parallel and has dedicated caches for efficient data access.
NextSilicon's technology is designed to be compatible, portable, and flexible, offering better power efficiency and throughput than GPUs while maintaining single-threaded performance comparable to FPGAs. The company's focus on HPC and its innovative architecture make it a promising player in the computing industry, with potential applications in various fields.
